Pipeline modular multiplier

Abstract

Various approaches of multiplying multi-bit numbers modulo are considered. The algorithm of multiplication of numbers is presented, where the process of multiplication modulo is divided into steps and at each step the operation of multiplication is combined with the operation of reducing numbers modulo forms a partial remainder. The circuit solutions for pipeline multiplication of numbers modulo with the analysis of the least significant bits of the multiplier are considered. The proposed modular multiplier does not require preliminary calculations and the calculation results do not go beyond the bit grid of the module. To evaluate the effectiveness, the ratios are used, by which the timing parameters of the multipliers are determined without a pipeline and using a pipeline. Algorithmic validation and verification of the pipeline modular multiplier was carried out on a Nexys 4 board based on the FPGA Artix-7 from Xilinx. Verilog HDL is used to describe the circuit of the pipeline multiplier. The results of a timing simulation of the device are presented in the form of time diagrams, confirming the correct operation of the device.